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WILSONVILLE, Ore.--(BUSINESS WIRE)--June 11, 2001--Mentor Graphics Corp. (Nasdaq:MENT), today announced that it will be first to provide a co-verification processor support package (PSP) for the new MIPS32(TM) 4KE(TM) family of embedded processor cores from MIPS® Technologies (Nasdaq:MIPS; Nasdaq:MIPSB - ).

Co-verification with the Mentor Graphics® Seamless® Co-Verification Environment(TM) (CVE) tool will enable developers integrating the latest MIPS32 core into System-on-Chip (SoC) designs to validate hardware and software interfaces prior to chip fabrication. The software helps to avoid costly and time-consuming silicon re-spins in the time-constrained digital consumer and networking markets.

The PSP for the MIPS32 4KE core incorporates an Instruction Set Simulator and Bus Interface Models from MIPS Technologies. The PSP is integrated with the high-level, multi-core Mentor Graphics XRAY® Debugger and works with all popular logic simulation platforms, including the ModelSim® tool from Model Technology, a Mentor Graphics company. Seamless also complements readily available, general-purpose MIPS processor development tools. The MIPS32 4KEc core is targeted at digital consumer applications, from ultra low-power mobile devices to emerging home networking products.

``MIPS Technologies and our licensees rely on readily available embedded development tools to help preserve the time-to-market advantages of our cores,'' said Mark Pittman, director of product marketing at MIPS Technologies. ``Mentor Graphics consistently provides co-verification models that developers of MIPS-based(TM) integrated circuits can use to verify the functional performance of their applications in a virtual prototype. Shortening our customers' verification cycles allows them to focus on product differentiators that give them a competitive advantage.''

``Digital consumer and network applications are two of the most cost- and time-sensitive markets in the semiconductor industry,'' said Serge Leef, general manager of the SoC Verification Division at Mentor Graphics. ``To ease the verification bottleneck that threatens rapid time-to-market, Mentor continues to release co-verification models in lockstep with all important processor architectures.''

The high-performance capabilities and low-power requirements of the MIPS32 4KE family offer the highest Dhrystone MIPS/MHz performance available in a synthesizable 32-bit core. The MIPS32 4KE cores also provides configurable features that increase performance while reducing die size and power consumption, and ultimately total system cost. Features such as 0 - 128 kilobytes of cache and a co-processor interface allow users to easily configure a 4KE core to maximize performance in their SoC applications.

Availability

The Mentor Graphics Seamless PSP for MIPS Technologies MIPS32 4KE core will be available in Q3 starting at $30,000 base on HP and Sun workstations. For more information, or to register for upcoming SoC workshops and seminars, visit the Seamless web site at www.mentor.com/seamless.

About Seamless

Combining the best in embedded software development tools with logic simulation, the Mentor Graphics Seamless co-verification environment delivers high performance co-verification months before a hardware prototype can be built. The Seamless environment enables software and hardware development to be parallel activities, removing the software from the critical path, and reducing the risk of hardware prototype iterations resulting from integration errors. User-controlled optimizations boost performance by isolating the logic simulator from software-intensive operations such as block memory transfers and algorithmic routines.

About Mentor Graphics

Mentor Graphics Corporation (Nasdaq:MENT) is a world leader in electronic hardware and software design solutions, providing products and consulting services for the world's most successful electronics and semiconductor companies. Established in 1981, the company reported revenues over the last 12 months of more than $600 million and employs approximately 2,850 people worldwide. Corporate headquarters are located at 8005 S.W. Boeckman Road, Wilsonville, Oregon 97070-7777; Silicon Valley headquarters are located at 1001 Ridder Park Drive, San Jose, California 95131-2314. World Wide Web site: www.mentor.com.

Mentor Graphics, Seamless, ModelSim and XRAY are registered trademarks of Mentor Graphics Corporation. Co-Verification Environment and CVE are trademarks of Mentor Graphics. MIPS® is a registered trademark and MIPS32(TM) and MIPS32(TM) 4KE(TM) are trademarks of MIPS Technologies, Inc. All other company or product names are the registered trademarks or trademarks of their respective owners.

     Mentor Graphics Corporation
     Wendy Slocum, 503/685-1145
     wendy_slocum@mentor.com
     or
     Benjamin Group/BSMG Worldwide
     Jeremiah Glodoveza, 415/352-2628 ext. 559
     jeremiah@benjamingroup.com